94 lines
1.8 KiB
Plaintext
94 lines
1.8 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-23083092
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// Cuda compilation tools, release 9.1, V9.1.85
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// Based on LLVM 3.4svn
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//
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.version 6.1
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.target sm_30
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 8 .b8 cs[32];
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.visible .entry __raygen__oxMain(
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)
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{
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.reg .pred %p<3>;
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.reg .b16 %rs<12>;
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.reg .f32 %f<26>;
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.reg .b32 %r<9>;
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.reg .b64 %rd<13>;
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// inline asm
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call (%r1), _optix_get_launch_index_x, ();
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// inline asm
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// inline asm
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call (%r2), _optix_get_launch_index_y, ();
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// inline asm
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ld.const.u64 %rd3, [cs+8];
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cvta.to.global.u64 %rd4, %rd3;
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ld.const.v2.u32 {%r4, %r5}, [cs+24];
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mad.lo.s32 %r7, %r4, %r2, %r1;
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cvt.u64.u32 %rd1, %r7;
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mul.wide.u32 %rd5, %r7, 16;
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add.s64 %rd6, %rd4, %rd5;
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ld.global.v4.f32 {%f10, %f24, %f12, %f13}, [%rd6];
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setp.eq.s32 %p1, %r5, 1;
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selp.f32 %f23, %f12, %f10, %p1;
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selp.f32 %f25, %f10, %f12, %p1;
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setp.eq.s32 %p2, %r5, 0;
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ld.const.u64 %rd2, [cs];
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@%p2 bra BB0_2;
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cvta.to.global.u64 %rd7, %rd2;
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shl.b64 %rd8, %rd1, 3;
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add.s64 %rd9, %rd7, %rd8;
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ld.global.v4.u16 {%rs4, %rs5, %rs6, %rs7}, [%rd9];
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// inline asm
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{ cvt.f32.f16 %f16, %rs4;}
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// inline asm
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// inline asm
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{ cvt.f32.f16 %f17, %rs5;}
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// inline asm
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// inline asm
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{ cvt.f32.f16 %f18, %rs6;}
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// inline asm
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min.f32 %f23, %f23, %f16;
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min.f32 %f24, %f24, %f17;
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min.f32 %f25, %f25, %f18;
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BB0_2:
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cvta.to.global.u64 %rd10, %rd2;
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shl.b64 %rd11, %rd1, 3;
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add.s64 %rd12, %rd10, %rd11;
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mov.f32 %f22, 0f3F800000;
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// inline asm
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{ cvt.rn.f16.f32 %rs11, %f22;}
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// inline asm
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// inline asm
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{ cvt.rn.f16.f32 %rs10, %f25;}
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// inline asm
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// inline asm
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{ cvt.rn.f16.f32 %rs9, %f24;}
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// inline asm
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// inline asm
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{ cvt.rn.f16.f32 %rs8, %f23;}
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// inline asm
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st.global.v4.u16 [%rd12], {%rs8, %rs9, %rs10, %rs11};
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ret;
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}
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